This disclosure relates to data processing and storage, and more specifically, to management of a data storage system, such as a flash memory system, utilizing a merged background management process.
Flash memory is a non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor. As is well known in the art, flash memory is inherently susceptible to bit errors, including program disturbs, read disturbs, retention errors (i.e., errors attributable to decay of the gate charge of programmed cells over time), and/or endurance errors (i.e., errors attributable to damage to the gate dielectric due to the number of cell program/erase (PE) cycles to which the cell is subjected). Consequently, data storage systems employing flash memory as a storage media generally implement multiple flash management functions to address the inherent error characteristics of flash memory. Existing systems commonly integrate at least some of these flash management functions into the data path (e.g., error correcting code (ECC) encoding and RAID-like data protection schemes), while other flash management functions operate in the background independently of any external requests for the data stored in the flash memory. Examples of background flash management functions common in enterprise-class flash arrays include read sweeping, which entails reading individual flash pages to detect bit errors, and wear leveling, which seeks to equalize the program/erase cycle counts for all flash pages.
As with other memory technologies, succeeding generations of flash memory achieve ever increasing cell densities, resulting in improved cost per byte of storage. However, the succeeding generations of flash memory are inherently more prone to bit errors due to the increased cell densities. Error rates tend to be even more aggravated in multi-level cell (MLC) and other flash technologies that store two or more bits of data per cell. Consequently, to achieve a given level of reliability, the number of discrete flash management functions and the processing required to perform the flash management functions tend to increase in each generation of flash memory.